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datasheet 9dbv0231 revision f 04/28/16 1 ?2016 integrated device technology, inc. 2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 9dbv0231 description the 9dbv0231 is a member of idt's 1.8v very-low-power (vlp) pcie family. the device has 2 output enables for clock management. recommended application 1.8v pcie gen1/2/3 zero-del ay/fan-out buffer (zdb/fob) output features ? 2 ? 1-200mhz low-power (lp) hcsl dif pairs key specifications ? dif cycle-to-cycle jitter <50ps ? dif output-to-output skew <50ps ? dif additive phase jitter is <100fs rms for pcie gen3 ? dif additive phase jitter <300fs rms (12k-20mhz) features/benefits ? lp-hcsl outputs; save 4 resistors compared to standard hcsl outputs ? 35mw typical power consumption in pll mode; reduced thermal concerns ? spread spectrum (ss) compatible; allows use of ss for emi reduction ? oe# pins; support dif power management ? hcsl compatible differential input; can be driven by common clock sources ? smbus-selectable features; opt imize signal integrity to application ? slew rate for each output ? differential output amplitude ? pin/software selectable pll bandwidth and pll bypass; minimize phase jitter for each application ? outputs blocked until pll is locked; clean system start-up ? device contains default confi guration; smbus interface not required for device control ? 3.3v tolerant smbus interface works with legacy controllers ? space saving 24-pin 4x4mm vfqfpn; minimal board space block diagram , control logic ^vhibw_bypm_lobw# ^ckpwrgd_pd# sdata_3.3 ss- compatible pll voe(1:0)# sclk_3.3 clk_in c l k _ i n # 2 dif0 dif1
2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 2 revision f 04/28/16 9dbv0231 datasheet pin configuration power management table smbus address table power connections frequency select table pll operating mode fb_dnc ^vhibw_bypm_lobw# ^ckpwrgd_pd# gnd vddo1.8 voe1# 24 23 22 21 20 19 fb_dnc# 1 18 dif1# vddr1.8 2 17 dif1 clk_in 3 16 vdda1.8 clk_in# 4 15 gnda gndr 5 14 dif0# gnddig 6 13 dif0 7 8 9 10 11 12 vdddig1.8 sclk_3.3 sdata_3.3 gnd vddo1.8 voe0# 24-pin vfqfpn, 4x4 mm, 0.5mm pitch 9dbv0231 epad is gnd ^ prefix indicates internal 120kohm pull up resistor ^v prefix indicates internal 120kohm pull up and pull down resistor (biased to vdd/2) v prefix indicates internal 120kohm pull down resistor true o/p comp. o/p 0 x x x low low off 1 running 0 x low low on 1 1 running 1 0 running running on 1 1 running 1 1 low low on 1 ckpwrgd_pd# smbus oex bit 1. if bypass mode is selected, the pll will be off, and outputs will be running. clk_in oex# pin pll difx address 1101101 + read/write bit x vdd gnd 25 76 11,20 10,21 16 15 input receiver analo g digital power dif outputs pll analog description pin number fsel b y te3 [ 4:3 ] clk_in ( mhz ) difx ( mhz ) 00 (default) 100.00 clk_in 01 50.00 clk_in 10 125.00 clk_in 11 reserved reserved hibw_bypm_lobw# mode byte1 [7:6] readback byte1 [4:3] control 0 pll lo bw 00 00 mbypass0101 1 pll hi bw 11 11
revision f 04/28/16 3 2-output 1.8v pc ie gen1/2/3 zero delay / fanout buffer 9dbv0231 datasheet pin descriptions pin# pin name type description 1 fb_dnc# dnc complement clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 2 vddr1.8 pwr 1.8v power for differential input clock (receiver). this vdd should be treated as an analog power rail and filtered appropriately. 3 clk_in in true input for differential reference clock. 4 clk_in# in complementary input for differential reference clock. 5 gndr gnd analog ground pin for the differential input (receiver) 6 gnddig gnd ground pin for digital circuitry 7 vdddig1.8 pwr 1.8v digital power (dirty power) 8 sclk_3.3 in clock pin of smbus circuitry, 3.3v tolerant. 9 sdata_3.3 i/o data pin for smbus circuitry, 3.3v tolerant. 10 gnd gnd ground pin. 11 vddo1.8 pwr power supply for outputs, nominally 1.8v. 12 voe0# in active low input for enabling dif pair 0. this pin has an internal pull- down. 1 =disable outputs, 0 = enable outputs 13 dif0 out differential true clock output 14 dif0# out differential complementary clock output 15 gnda gnd ground pin for the pll core. 16 vdda1.8 pwr 1.8v power for the pll core. 17 dif1 out differential true clock output 18 dif1# out differential complementary clock output 19 voe1# in active low input for enabling dif pair 1. this pin has an internal pull- down. 1 =disable outputs, 0 = enable outputs 20 vddo1.8 pwr power supply for outputs, nominally 1.8v. 21 gnd gnd ground pin. 22 ^ckpwrgd_pd# in input notifies device to sample latched inputs and start up on first high assertion. low enters power down mode, subsequent high assertions exit power down mode. this pin has internal pull-up resistor. 23 ^vhibw_bypm_lobw# latched in trilevel input to select high bw, bypass or low bw mode. see pll operating mode table for details. 24 fb_dnc dnc true clock of differential feedback. the feedback output and feedback input are connected internally on this pin. do not connect anything to this pin. 25 epad gnd connect epad to ground. note: dnc indicates do not connect anything to this pin.
2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 4 revision f 04/28/16 9dbv0231 datasheet test loads alternate terminations the 9dbv family can easily drive lvpecl, lvds, and cml logic. see ?an-891 driving lvpecl, lv ds, and cml logic with idt's "universal" low-power hcsl outputs? for details. differential output terminations rs zo units 33 100 27 85 ohms rs rs low-power hcsl differential output test load 2pf 2pf l zo=100ohm device l = 5 inches
revision f 04/28/16 5 2-output 1.8v pc ie gen1/2/3 zero delay / fanout buffer 9dbv0231 datasheet absolute maximum ratings stresses above the ratings listed below can cause permanent damage to the 9dbv023 1. these ratings, which are standard values for idt commercially rated parts, ar e stress ratings only. functional operati on of the device at these or any other conditions above those indicated in the operational sections of th e specifications is not implied. exposure to absolute maximum rating conditions for ex tended periods can affect product reliability. electrical param eters are gu aranteed only over the recommended operating temperature range. electrical characteristi cs?clock input parameters parameter symbol conditions min typ max units notes 1.8v supply voltage vddxx applies to all vdd pins -0.5 2.5 v 1,2 input voltage v in -0.5 v dd +0.5v v 1, 3 input high voltage, smbus v ihsmb smbus clock and data pins 3.6v v 1 storage temperature ts -65 150 c 1 junction temperature tj 125 c 1 input esd protection esd prot human body model 2000 v 1 1 guaranteed by design and characterization, not 100% tested in production. 2 operation under these conditions is neither implied nor guaranteed. 3 not to exceed 2.5v. ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes input common mode voltage - dif_in v com common mode input voltage 150 1000 mv 1 input swing - dif_in v swing differential value 300 1450 mv 1 input slew rate - dif_in dv/dt measured differentially 0.4 8 v/ns 1,2 input leakage current i in v in = v dd , v in = gnd -5 5 ua input duty cycle d tin measurement from differential wavefrom 45 55 % 1 input jitter - cycle to cycle j di fi n differential measurement 0 125 ps 1 1 guaranteed by desi g n and characterization, not 100% tested in production. 2 slew rate measured through +/-75mv window centered around differential zero
2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 6 revision f 04/28/16 9dbv0231 datasheet electrical characteristics?input/supply /common parameters?normal operating conditions ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes supply voltage vddx supply voltage for core and analog 1.7 1.8 1.9 v commmercial range 0 25 70 c industrial range -40 25 85 c input high voltage v ih single-ended inputs, except smbus 0.75 v dd v dd + 0.3 v input mid voltage v im single-ended tri-level inputs ('_tri' suffix) 0.4 v dd 0.6 v dd v input low voltage v il single-ended inputs, except smbus -0.3 0.25 v dd v i in single-ended inputs, v in = gnd, v in = vdd -5 5 ua i inp single-ended inputs v in = 0 v; inputs with internal pull-up resistors v in = vdd; inputs with internal pull-down resistors -200 200 ua f ib yp bypass mode 1 200 mhz 2 f i p ll 100mhz pll mode 50 100.00 140 mhz 2 f i p ll 125mhz pll mode 62.5 125.00 175 mhz 2 f i p ll 50mhz pll mode 25 50.00 65 mhz 2 pin inductance l p in 7nh1 c in logic inputs, except dif_in 1.5 5 pf 1 c indif_in dif_in differential clock inputs 1.5 2.7 pf 1,5 c out output pin capacitance 6 pf 1 clk stabilization t stab from v dd power-up and after input clock stabilization or de-assertion of pd# to 1st clock 1ms1,2 input ss modulation frequency pcie f modi npci e allowable frequency for pcie applications (triangular modulation) 30 33 khz input ss modulation frequency non-pcie f modi n allowable frequency for non-pcie applications (triangular modulation) 066khz oe# latency t latoe# dif start after oe# assertion dif stop after oe# deassertion 1 3 clocks 1,3 tdrive_pd# t drvpd dif output enable after pd# de-assertion 300 us 1,3 tfall t f fall time of single-ended control inputs 5 ns 2 trise t r rise time of single-ended control inputs 5 ns 2 smbus input low voltage v ilsmb v ddsmb = 3.3v, see note 4 for v ddsmb < 3.3v 0.6 v smbus input high voltage v ihsmb v ddsmb = 3.3v, see note 5 for v ddsmb < 3.3v 2.1 3.6 v 4 smbus output low voltage v olsmb @ i pullup 0.4 v smbus sink current i pullup @ v ol 4ma nominal bus voltage v ddsmb bus voltage 1.7 3.6 v sclk/sdata rise time t rsmb (max vil - 0.15) to (min vih + 0.15) 1000 ns 1 sclk/sdata fall time t fsmb (min vih + 0.15) to (max vil - 0.15) 300 ns 1 smbus operating frequency f maxsmb maximum smbus operating frequency 400 khz 6 1 guaranteed by design and characterization, not 100% tested in production. 2 control input must be monotonic from 20% to 80% of input swing. 3 time from deassertion until outputs are >200 mv 5 dif_in input 6 the differential input clock must be runnin g for the smbus to be active 4 for v ddsmb < 3.3v, v ihsmb >= 0.8xv ddsmb input current input frequency capacitance ambient operating temperature t amb
revision f 04/28/16 7 2-output 1.8v pc ie gen1/2/3 zero delay / fanout buffer 9dbv0231 datasheet electrical characteristics?dif 0.7v low power hcsl outputs electrical characteristi cs?current consumption ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes dv/dt scope averaging on, fast setting 1.9 3.2 4 v/ns 1,2,3 dv/dt scope averaging on, slow setting 1.4 2.3 3.3 v/ns 1,2,3 slew rate matching ? dv/dt slew rate matching, scope averaging on 5 20 % 1,2,4 voltage high v hi gh 660 779 850 7 voltage low v low -150 21 150 7 max voltage vmax 835 1150 7 min voltage vmin -300 -42 7 crossing voltage (abs) vcross_abs scope averaging off 250 409 550 mv 1,5 crossing voltage (var) -vcross scope averaging off 14 140 mv 1,6 2 measured from differential waveform slew rate statistical measurement on single-ended signal using oscilloscope math function. (scope averaging on) mv measurement on single ended signal using absolute value. (scope averaging off) mv 7 at default smbus settings. 1 guaranteed by design and characterization, not 100% tested in production. 3 slew rate is measured through the vswing voltage range centered around differential 0v. this results in a +/-150mv window arou nd differential 0v. 4 matching applies to rising edge rate for clock and falling edge rate for clock#. it is measured using a +/-75mv window centered on the average cross point where clock rising meets clock# falling. the median cross point is used to calculate the voltage thresh olds the oscilloscope is to use for the edge rate calculations. 5 vcross is defined as voltage where clock = clock# measured on a component test board and only applies to the differential risi ng edge (i.e. clock rising and clock# falling). 6 the total variation of all vcross measurements in any particular system. note that this is a subset of vcross_min/max (vcross absolute) allowed. the intent is to limit vcross induced modulation by setting -vcross to be smaller than vcross absolute. ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes i dda vdda+vddr, pll mode, @100mhz 4.4 6 ma 1 i dd vdd, all outputs active @100mhz 14.2 18 ma 1 i ddap d vdda+vddr, pll mode, @100mhz 0.014 1 ma 1, 2 i ddpd vdd, outputs low/low 0.9 1.4 ma 1, 2 1 guaranteed by design and characterization, not 100% tested in production. 2 input clock stopped. operating supply current powerdown current
2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 8 revision f 04/28/16 9dbv0231 datasheet electrical characteristics?ou tput duty cycle, jitter, sk ew and pll characteristics electrical characteristics? phase jitter parameters ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max units notes -3db point in high bw mode 2 2.7 4 mhz 1,5 -3db point in low bw mode 1 1.4 2 mhz 1,5 pll jitter peaking t jpeak peak pass band gain 1.05 2 db 1 duty cycle t d c measured differentially, pll mode 45 50 55 % 1 duty cycle distortion t dcd measured differentially, bypass mode @100mhz -1 -0.1 1 % 1,3 t p dbyp bypass mode, v t = 50% 2600 3370 4200 ps 1 t p dpll pll mode v t = 50% 0 112 200 ps 1,4 skew, output to output t sk3 v t = 50% 33 50 ps 1,4 pll mode 13 50 ps 1,2 additive jitter in bypass mode 0.1 5 ps 1,2 1 guaranteed by design and characterization, not 100% tested in production. 2 measured from differential waveform 3 duty cycle distortion is the difference in duty cycle betw een the output and the input clock when the device is operated in bypass mode. 4 all outputs at default slew rate 5 the min/typ/max values of each bw setting track each other, i.e., low bw max will never occur with hi bw min. pll bandwidth bw skew, input to output jitter, cycle to cycle t jcyc-cyc ta = t amb, supply voltages per normal operation conditions, see test loads for loading conditions parameter symbol conditions min typ max industry limit units notes t jp hpcieg1 pcie gen 1 32 52 86 ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz 0.8 1.4 3 ps (rms) 1,2,3,5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 2.4 2.5 3.1 ps (rms) 1,2,3,5 t jphpcieg3 pcie gen 3 (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.5 0.6 1 ps (rms) 1,2,3,5 t jphsgmii 125mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 1.9 2 na ps (rms) 1,6 t jphpcieg1 pcie gen 1 0.1 5 n/a ps (p-p) 1,2,3,5 pcie gen 2 lo band 10khz < f < 1.5mhz 0.2 0.3 n/a ps (rms) 1,2,3,4, 5 pcie gen 2 high band 1.5mhz < f < nyquist (50mhz) 0.00 0.1 n/a ps (rms) 1,2,3,4 t jphpcieg3 pcie gen 3 (pll bw of 2-4 or 2-5mhz, cdr = 10mhz) 0.00 0.1 n/a ps (rms) 1,2,3,4 t jphsgmii 125mhz, 1.5mhz to 10mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 165 200 n/a ps (rms) 1,6 t jphsgmii 125mhz, 12khz to 20mhz, -20db/decade rollover < 1.5mhz, -40db/decade rolloff > 10mhz 251 300 n/a ps (rms) 1,6 1 guaranteed by design and characterization, not 100% tested in production. 4 for rms figures, additive jitter is calculated by solving the following equation: additive jitter = sqrt[(total jitter)^2 - (i nput jitter)^2] 5 driven by 9fg432 or equivalent 6 rohde&schartz sma100 phase jitter, pll mode t jphpcieg2 t jphpcieg2 2 see http://www.pcisig.com for complete specs 3 sample size of at least 100k cycles. this figures extrapolates to 108ps pk-pk @ 1m cycles for a ber of 1-12. additive phase jitter, bypass mode
revision f 04/28/16 9 2-output 1.8v pc ie gen1/2/3 zero delay / fanout buffer 9dbv0231 datasheet additive phase jitter plo t: 125m (12khz to 20mhz) rms ? additve ? jitter: ? 251fs
2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 10 revision f 04/28/16 9dbv0231 datasheet general smbus serial interface information how to write ? controller (host) sends a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) sends the byte count = x ? idt clock will acknowledge ? controller (host) starts sending byte n through byte n+x-1 ? idt clock will acknowledg e each byte one at a time ? controller (host) sends a stop bit note: smbus address is 1101101x, where x is the read/write bit. how to read ? controller (host) will send a start bit ? controller (host) sends the write address ? idt clock will acknowledge ? controller (host) sends the beginning byte location = n ? idt clock will acknowledge ? controller (host) will send a separate start bit ? controller (host) sends the read address ? idt clock will acknowledge ? idt clock will send the data byte count = x ? idt clock sends byte n+x-1 ? idt clock sends byte 0 through byte x (if x (h) was written to byte 8) ? controller (host) will need to acknowledge each byte ? controller (host) will send a not acknowledge bit ? controller (host) will send a stop bit index block write operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack data byte count = x ack beginning byte n x byte ack o oo oo o byte n + x - 1 ack pstop bit index block read operation controller (host) idt (slave/receiver) tstart bit slave address wr write ack beginning byte = n ack rt repeat start slave address rd read ack data byte count=x ack x byte beginning byte n ack o oo oo o byte n + x - 1 n not acknowledge pstop bit
revision f 04/28/16 11 2-output 1.8v pc ie gen1/2/3 zero delay / fanout buffer 9dbv0231 datasheet smbus table: output enable register 1 byte 0 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 dif oe1 output enable rw low/low enabled 1 bit 4 1 bit 3 dif oe0 output enable rw low/low enabled 1 bit 2 1 bit 1 1 bit 0 1 1. a low on these bits will overide the oe# pin and force the differential output low/low smbus table: pll operating mode and output amplitude control register byte 1 name control function type 0 1 default bit 7 pllmoderb1 pll mode readback bit 1 r latch bit 6 pllmoderb0 pll mode readback bit 0 r latch bit 5 pllmode_swcntrl enable sw control of pll mode rw values in b1[7:6] set pll mode values in b1[4:3] set pll mode 0 bit 4 pllmode1 pll mode control bit 1 rw 1 0 bit 3 pllmode0 pll mode control bit 0 rw 1 0 bit 2 1 bit 1 amplitude 1 rw 00 = 0.6v 01 = 0.7v 1 bit 0 amplitude 0 rw 10= 0.8v 11 = 0.9v 0 1. b1[5] must be set to a 1 for these bits to have any effect on the part. smbus table: dif slew rate control register byte 2 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 slewratesel dif1 slew rate selection rw slow setting fast setting 1 bit 4 1 bit 3 slewratesel dif0 slew rate selection rw slow setting fast setting 1 bit 2 1 bit 1 1 bit 0 1 smbus table: frequency select control register byte 3 name control function type 0 1 default bit 7 1 bit 6 1 bit 5 freq_sel_en enable sw selection of frequency rw sw frequency change disabled sw frequency change enabled 0 bit 4 fsel1 freq. select bit 1 rw 1 0 bit 3 fsel0 freq. select bit 0 rw 1 0 bit 2 1 bit 1 1 bit 0 slewratesel fb adjust slew rate of fb rw slow setting fast setting 1 1. b3[5] must be set to a 1 for these bits to have any effect on the part. byte 4 is reserved and reads back 'hff controls output amplitude reserved reserved see pll operating mode table reserved reserved reserved see frequency select table reserved reserved reserved reserved reserved see pll operating mode table reserved reserved reserved reserved reserved reserved reserved
2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 12 revision f 04/28/16 9dbv0231 datasheet smbus table: revision and vendor id register byte 5 name control function type 0 1 default bit 7 rid3 r 0 bit 6 rid2 r 0 bit 5 rid1 r 0 bit 4 rid0 r 0 bit 3 vid3 r 0 bit 2 vid2 r 0 bit 1 vid1 r 0 bit 0 vid0 r 1 smbus table: device type/device id byte 6 name control function type 0 1 default bit 7 device type1 r 0 bit 6 device type0 r 1 bit 5 device id5 r 0 bit 4 device id4 r 0 bit 3 device id3 r 0 bit 2 device id2 r 0 bit 1 device id1 r 1 bit 0 device id0 r 0 smbus table: byte count register byte 7 name control function type 0 1 default bit 7 0 bit 6 0 bit 5 0 bit 4 bc4 rw 0 bit 3 bc3 rw 1 bit 2 bc2 rw 0 bit 1 bc1 rw 0 bit 0 bc0 rw 0 a rev = 0000 revision id 0001 = idt device type writing to this register will configure how many bytes will be read back, default is = 8 bytes. vendor id 000100 binary or 02 hex 00 = fgx, 01 = dbx, 10 = dmx, 11= reserved device id reserved reserved byte count programming reserved
revision f 04/28/16 13 2-output 1.8v pc ie gen1/2/3 zero delay / fanout buffer 9dbv0231 datasheet marking diagrams notes: 1. ?lot? is the lot sequence number. 2. yyww is the last two digits of the ye ar and week that the part was assembled. 3. line 2: truncated part number 4. ?l? denotes rohs compliant package. 5. ?i? denotes industrial temperature range device. thermal characteristics lot 031ail yyww lot 031al yyww parameter symbol conditions pkg typ value units notes jc junction to case 62 c/w 1 c/w 1 c/w 1 c/w 1 c/w 1 ja5 junction to air, 5 m/s air flow 38 c/w 1 1 epad soldered to board nlg20 nlg24 thermal resistance
2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 14 revision f 04/28/16 9dbv0231 datasheet package outline and dimensions (nlg24)
revision f 04/28/16 15 2-output 1.8v pc ie gen1/2/3 zero delay / fanout buffer 9dbv0231 datasheet package outline and dimensions (nlg24), cont.
2-output 1.8v pcie gen1/2/3 zero delay / fanout buffer 16 revision f 04/28/16 9dbv0231 datasheet ordering information "lf" suffix to the part number are the pb-free configuration and are rohs compliant. ?a? is the device revision designator (will not correlate with the datasheet revision). revision history part / order number shipping packaging package temperature 9dbv0231aklf tubes 24-pin vfqfpn 0 to +70 c 9dbv0231aklft tape and reel 24-pin vfqfpn 0 to +70 c 9DBV0231AKILF tubes 24-pin vfqfpn -40 to +85 c 9DBV0231AKILFt tape and reel 24-pin vfqfpn -40 to +85 c rev. initiator issue date description page # a rdw 8/13/2012 1. updated electrical characteristics tables. 2. move to final. 5-8 b rdw 9/16/2014 1. changed vih min. from 0.65*vdd to 0.75*vdd 2. changed vil max. from 0.35*vdd to 0.25*vdd 3. added missing mid-level input voltage spec (vim) of 0.4*vdd to 0.6*vdd. 4. changed shipping packaging from "trays" to "tubes". 5. reformatted to new template various c rdw 4/3/2015 1. updated block diagram with new format showing individual outputs instead of bussed outputs. 2. updated pin out and pin descriptions to show epad on package connected to ground. 3. updated front page text to standard format for these devices. added explicit bullet indicated spread spectrum compatibilty. changed data sheet title, etc. 4. added additive phase jitter plot and updated phase jitter spec table. 1-4,9 d rdw 8/10/2015 1. replaced "driving lvds" with "alternate terminations", adding reference to an-891. 2. updated "clock input parameters table" correcting inconsistency with pcie sig specifications. 3. widened allowable input frequency at each pll mode frequency. 4. updated nlg24 package drawing with actual package info instead of g eneric drawin g . 4,5,6,14 e rdw 11/5/2015 1. minor typographical corrections throughout the data sheet 2. updated test load diagram to generic diagram. length of test load listed outside the drawing. 3. minor updates to electrical tables for formatting. removed schmitt trigger info and output high/low voltage specifications for single-ended outputs, since this part does not have any. 4. "low-power hcsl outputs" table: corrected inversion of slew rate setting with specifications. changed reference from 2 v/ns and 3 v/ns to slow setting and fast setting. also change references in smbus bytes[3:2] 5. "low-power hcsl outputs" table: removed vswing parameter since this is an input parameter and is covered in "clock input parameters" table. 6. reduced current consumption limits. 7. minor updates to other electrical tables. various ,4-8,11 f rdw 4/28/2016 1. updated max frequency of 100mhz pll mode to 140mhz 2. updated max frequency of 125mhz pll mode to 175mhz 3. updated max frequency of 50mhz pll mode to 65mhz 6
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